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rtl_rtl8139_drv.h File Reference

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/in.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/mii.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/highmem.h>
#include <asm/irq.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <rtl_sched.h>
#include <signal.h>
#include <time.h>
#include <rtl_sync.h>
#include <rtl_core.h>
#include <rtl_printf.h>
#include <rtl_posixio.h>
#include <sys/mman.h>
#include <errno.h>
#include <unistd.h>
#include <rtl.h>
#include <rtl_malloc.h>
#include <rtl_sema.h>
#include "memcopy.h"

Include dependency graph for rtl_rtl8139_drv.h:

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Data Structures

struct  ring_info
struct  rtl8139_private
struct  rx_buffer_t
struct  rx_slot_t

Defines

#define DRV_NAME   "rtl8139"
#define DRV_VERSION   "0.1"
#define DRV_RELDATE   " 4 2003"
#define RTL_W8_F(reg, val8)   do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
#define RTL_W16_F(reg, val16)   do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
#define RTL_W32_F(reg, val32)   do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
#define RTL_W8   RTL_W8_F
#define RTL_W16   RTL_W16_F
#define RTL_W32   RTL_W32_F
#define RTL_R8(reg)   readb (ioaddr + (reg))
#define RTL_R16(reg)   readw (ioaddr + (reg))
#define RTL_R32(reg)   ((unsigned long) readl (ioaddr + (reg)))
#define MAX_THREADS   10
#define RTL8139_VENDOR_ID   0x10EC
#define RTL8139_DEVICE_ID   0X8139
#define PKT_BUF_SZ   1536
#define RX_BUF_LEN_IDX   2
#define RX_BUF_LEN   (8192 << RX_BUF_LEN_IDX)
#define RX_BUF_PAD   16
#define RX_BUF_WRAP_PAD   2048
#define RX_BUF_TOT_LEN   (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
#define MAX_ADDR_LEN   8
#define NUM_TX_DESC   4
#define MAX_ETH_FRAME_SIZE   1536
#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE
#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)
#define NUM_TX_DESC   4
#define MAX_ETH_FRAME_SIZE   1536
#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE
#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)
#define TX_FIFO_THRESH   256
#define RX_FIFO_THRESH   6
#define RX_DMA_BURST   6
#define TX_DMA_BURST   6
#define TX_TIMEOUT   (6*HZ)
#define NUM_CP_TX_DESC   64
#define NUM_CP_RX_DESC   64
#define CP_RX_BUF_SIZE   2000
#define TX_RING_SIZE   16
#define RX_RING_SIZE   32
#define RTL_MIN_IO_SIZE   0x80
#define RTL8139B_IO_SIZE   256
#define RTL8129_CAPS   HAS_MII_XCVR
#define RTL8139_CAPS   HAS_CHIP_XCVR|HAS_LNK_CHNG
#define MAX_UNITS   8
#define MDIO_DIR   0x80
#define MDIO_DATA_OUT   0x04
#define MDIO_DATA_IN   0x02
#define MDIO_CLK   0x01
#define MDIO_WRITE0   (MDIO_DIR)
#define MDIO_WRITE1   (MDIO_DIR | MDIO_DATA_OUT)
#define rt_rtl8139_mdio_delay(mdio_addr)   readb(mdio_addr)
#define mdio_delay(mdio_addr)   readb(mdio_addr)
#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE
#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)
#define TX_FIFO_THRESH   256
#define PCI_DEBUG   0
#define EEPROM_CONTENTS_DEBUG   0
#define MAC_ADDRESS_DEBUG   0
#define FUNCTION_CALL_DEBUG   0
#define INITIALIZATION_DEBUG   0
#define RECEIVE_DEBUG   0
#define PACKET_DATA_DEBUG   0
#define INTERRUPT_DEBUG   0
#define TRANSMIT_DEBUG   0
#define ERROR_DEBUG   1
#define SIGALRM2   RTL_SIGUSR1
#define DEBUG(x, y)   if(x) printk y
#define MAX_RX_BUFFER_ENTRIES   50

Enumerations

enum  chip_t {
  CH_8139 = 0, CH_8139_K, CH_8139A, CH_8139B,
  CH_8130, CH_8139C, CH_8139CP
}
enum  { HAS_MII_XCVR = 0x010000, HAS_CHIP_XCVR = 0x020000, HAS_LNK_CHNG = 0x040000 }
enum  board_t {
  RTL8139 = 0, RTL8139_CB, SMC1211TX, DELTA8139,
  ADDTRON8139, DFE538TX, RTL8129
}
enum  RTL8139_registers {
  MAC0 = 0, MAR0 = 8, TxStatus0 = 0x10, TxAddr0 = 0x20,
  RxBuf = 0x30, RxEarlyCnt = 0x34, RxEarlyStatus = 0x36, ChipCmd = 0x37,
  RxBufPtr = 0x38, RxBufAddr = 0x3A, IntrMask = 0x3C, IntrStatus = 0x3E,
  TxConfig = 0x40, ChipVersion = 0x43, RxConfig = 0x44, Timer = 0x48,
  RxMissed = 0x4C, Cfg9346 = 0x50, Config0 = 0x51, Config1 = 0x52,
  FlashReg = 0x54, MediaStatus = 0x58, Config3 = 0x59, Config4 = 0x5A,
  HltClk = 0x5B, MultiIntr = 0x5C, TxSummary = 0x60, BasicModeCtrl = 0x62,
  BasicModeStatus = 0x64, NWayAdvert = 0x66, NWayLPAR = 0x68, NWayExpansion = 0x6A,
  FIFOTMS = 0x70, CSCR = 0x74, PARA78 = 0x78, PARA7c = 0x7c,
  Config5 = 0xD8, CPlusTxPoll = 0xD9, CPlusCmd = 0xE0, CPlusRxStartAddr = 0xE4,
  CPlusTxStartAddr = 0x20, CPlusEarlyTxThldReg = 0xEC
}
enum  ClearBitMasks { MultiIntrClear = 0xF000, ChipCmdClear = 0xE2, Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1) }
enum  ChipCmdBits { CmdReset = 0x10, CmdRxEnb = 0x08, CmdTxEnb = 0x04, RxBufEmpty = 0x01 }
enum  CPlusCmdBits { CPlusTxEnb = 0x01, CPlusRxEnb = 0x02, CPlusCheckSumEnb = 0x20 }
enum  CPlusRxStatusDesc {
  CPlusRxRES = 0x00100000, CPlusRxCRC = 0x00040000, CPlusRxRUNT = 0x00080000, CPlusRxRWT = 0x00200000,
  CPlusRxFAE = 0x08000000, CPlusRxIPchecksumBIT = 0x00008000, CPlusRxUDPIPchecksumBIT = 0x0000C000, CPlusRxTCPIPchecksumBIT = 0x0000A000,
  ProtocolType_NonIP = 0, ProtocolType_TCPIP = 1, ProtocolType_UDPIP = 2, ProtocolType_IP = 3
}
enum  CPlusTxChecksumOffload { CPlusTxIPchecksumOffload = 0x00040000, CPlusTxUDPchecksumOffload = 0x00020000, CPlusTxTCPchecksumOffload = 0x00010000 }
enum  IntrStatusBits {
  PCIErr = 0x8000, PCSTimeout = 0x4000, RxFIFOOver = 0x40, RxUnderrun = 0x20,
  RxOverflow = 0x10, TxErr = 0x08, TxOK = 0x04, RxErr = 0x02,
  RxOK = 0x01
}
enum  TxStatusBits {
  TxHostOwns = 0x2000, TxUnderrun = 0x4000, TxStatOK = 0x8000, TxOutOfWindow = 0x20000000,
  TxAborted = 0x40000000, TxCarrierLost = 0x80000000
}
enum  RxStatusBits {
  RxMulticast = 0x8000, RxPhysical = 0x4000, RxBroadcast = 0x2000, RxBadSymbol = 0x0020,
  RxRunt = 0x0010, RxTooLong = 0x0008, RxCRCErr = 0x0004, RxBadAlign = 0x0002,
  RxStatusOK = 0x0001
}
enum  rx_mode_bits {
  AcceptErr = 0x20, AcceptRunt = 0x10, AcceptBroadcast = 0x08, AcceptMulticast = 0x04,
  AcceptMyPhys = 0x02, AcceptAllPhys = 0x01
}
enum  tx_config_bits {
  TxIFG1 = (1 << 25), TxIFG0 = (1 << 24), TxLoopBack = (1 << 18) | (1 << 17), TxCRC = (1 << 16),
  TxClearAbt = (1 << 0), TxDMAShift = 8, TxVersionMask = 0x7C800000
}
enum  Config1Bits {
  Cfg1_PM_Enable = 0x01, Cfg1_VPD_Enable = 0x02, Cfg1_PIO = 0x04, Cfg1_MMIO = 0x08,
  Cfg1_LWAKE = 0x10, Cfg1_Driver_Load = 0x20, Cfg1_LED0 = 0x40, Cfg1_LED1 = 0x80
}
enum  RxConfigBits {
  RxCfgEarlyRxNone = 0, RxCfgEarlyRxShift = 24, RxCfgFIFOShift = 13, RxCfgFIFONone = (7 << RxCfgFIFOShift),
  RxCfgDMAShift = 8, RxCfgDMAUnlimited = (7 << RxCfgDMAShift), RxCfgRcv8K = 0, RxCfgRcv16K = (1 << 11),
  RxCfgRcv32K = (1 << 12), RxCfgRcv64K = (1 << 11) | (1 << 12), RxNoWrap = (1 << 7)
}
enum  CSCRBits {
  CSCR_LinkOKBit = 0x0400, CSCR_LinkChangeBit = 0x0800, CSCR_LinkStatusBits = 0x0f000, CSCR_LinkDownOffCmd = 0x003c0,
  CSCR_LinkDownCmd = 0x0f3c0
}
enum  Cfg9346Bits { Cfg9346_Lock = 0x00, Cfg9346_Unlock = 0xC0 }
enum  NegotiationBits {
  AutoNegotiationEnable = 0x1000, AutoNegotiationRestart = 0x0200, AutoNegoAbility10half = 0x21, AutoNegoAbility10full = 0x41,
  AutoNegoAbility100half = 0x81, AutoNegoAbility100full = 0x101
}
enum  MediaStatusBits { DuplexMode = 0x0100, Speed_10 = 0x08 }

Variables

struct {
   const char *   name
   u32   hw_flags
} __devinitdata []
struct {
   const char *   name
   u8   version
   u32   RxConfigMask
} rtl_chip_info []
int media [MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}
int full_duplex [MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}
char mii_2_8139_map [8]
const u16 rtl8139_intr_mask
const unsigned int rtl8139_rx_config
rx_buffer_t rx_buffer

Define Documentation

#define CP_RX_BUF_SIZE   2000
 

Definition at line 286 of file rtl_rtl8139_drv.h.

#define DEBUG (  x,
y   )     if(x) printk y
 

Definition at line 737 of file rtl_rtl8139_drv.h.

#define DRV_NAME   "rtl8139"
 

Definition at line 165 of file rtl_rtl8139_drv.h.

#define DRV_RELDATE   " 4 2003"
 

Definition at line 167 of file rtl_rtl8139_drv.h.

#define DRV_VERSION   "0.1"
 

Definition at line 166 of file rtl_rtl8139_drv.h.

#define EEPROM_CONTENTS_DEBUG   0
 

Definition at line 725 of file rtl_rtl8139_drv.h.

#define ERROR_DEBUG   1
 

Definition at line 733 of file rtl_rtl8139_drv.h.

#define FUNCTION_CALL_DEBUG   0
 

Definition at line 727 of file rtl_rtl8139_drv.h.

#define INITIALIZATION_DEBUG   0
 

Definition at line 728 of file rtl_rtl8139_drv.h.

#define INTERRUPT_DEBUG   0
 

Definition at line 731 of file rtl_rtl8139_drv.h.

#define MAC_ADDRESS_DEBUG   0
 

Definition at line 726 of file rtl_rtl8139_drv.h.

#define MAX_ADDR_LEN   8
 

Definition at line 243 of file rtl_rtl8139_drv.h.

#define MAX_ETH_FRAME_SIZE   1536
 

Definition at line 260 of file rtl_rtl8139_drv.h.

#define MAX_ETH_FRAME_SIZE   1536
 

Definition at line 260 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_rx_interrupt().

#define MAX_RX_BUFFER_ENTRIES   50
 

Definition at line 755 of file rtl_rtl8139_drv.h.

#define MAX_THREADS   10
 

Definition at line 230 of file rtl_rtl8139_drv.h.

#define MAX_UNITS   8
 

Definition at line 604 of file rtl_rtl8139_drv.h.

Referenced by start_up_rtl8139_device().

#define MDIO_CLK   0x01
 

Definition at line 617 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_mdio_read(), rt_rtl8139_mdio_sync(), and rt_rtl8139_mdio_write().

#define MDIO_DATA_IN   0x02
 

Definition at line 616 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_mdio_read().

#define MDIO_DATA_OUT   0x04
 

Definition at line 615 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_mdio_read().

#define mdio_delay (  mdio_addr   )     readb(mdio_addr)
 

Definition at line 622 of file rtl_rtl8139_drv.h.

#define MDIO_DIR   0x80
 

Definition at line 614 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_mdio_read().

#define MDIO_WRITE0   (MDIO_DIR)
 

Definition at line 618 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_mdio_write().

#define MDIO_WRITE1   (MDIO_DIR | MDIO_DATA_OUT)
 

Definition at line 619 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_mdio_sync(), and rt_rtl8139_mdio_write().

#define NUM_CP_RX_DESC   64
 

Definition at line 285 of file rtl_rtl8139_drv.h.

#define NUM_CP_TX_DESC   64
 

Definition at line 284 of file rtl_rtl8139_drv.h.

#define NUM_TX_DESC   4
 

Definition at line 257 of file rtl_rtl8139_drv.h.

#define NUM_TX_DESC   4
 

Definition at line 257 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_hw_start(), rt_rtl8139_init_ring(), rt_rtl8139_send_packet(), rt_rtl8139_tx_clear(), and rt_rtl8139_tx_interrupt().

#define PACKET_DATA_DEBUG   0
 

Definition at line 730 of file rtl_rtl8139_drv.h.

#define PCI_DEBUG   0
 

Definition at line 724 of file rtl_rtl8139_drv.h.

#define PKT_BUF_SZ   1536
 

Definition at line 235 of file rtl_rtl8139_drv.h.

#define RECEIVE_DEBUG   0
 

Definition at line 729 of file rtl_rtl8139_drv.h.

#define rt_rtl8139_mdio_delay (  mdio_addr   )     readb(mdio_addr)
 

Definition at line 621 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_mdio_read(), rt_rtl8139_mdio_sync(), and rt_rtl8139_mdio_write().

#define RTL8129_CAPS   HAS_MII_XCVR
 

Definition at line 318 of file rtl_rtl8139_drv.h.

#define RTL8139_CAPS   HAS_CHIP_XCVR|HAS_LNK_CHNG
 

Definition at line 319 of file rtl_rtl8139_drv.h.

#define RTL8139_DEVICE_ID   0X8139
 

Definition at line 233 of file rtl_rtl8139_drv.h.

Referenced by init_rtl8139_device().

#define RTL8139_VENDOR_ID   0x10EC
 

Definition at line 232 of file rtl_rtl8139_drv.h.

Referenced by init_rtl8139_device().

#define RTL8139B_IO_SIZE   256
 

Definition at line 316 of file rtl_rtl8139_drv.h.

Referenced by start_up_rtl8139_device().

#define RTL_MIN_IO_SIZE   0x80
 

Definition at line 315 of file rtl_rtl8139_drv.h.

Referenced by start_up_rtl8139_device().

#define RTL_R16 (  reg   )     readw (ioaddr + (reg))
 

Definition at line 222 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_close(), rt_rtl8139_hw_start(), and rt_rtl8139_interrupt().

#define RTL_R32 (  reg   )     ((unsigned long) readl (ioaddr + (reg)))
 

Definition at line 223 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_close(), rt_rtl8139_hw_start(), rt_rtl8139_set_rx_mode(), rt_rtl8139_tx_interrupt(), and start_up_rtl8139_device().

#define RTL_R8 (  reg   )     readb (ioaddr + (reg))
 

Definition at line 221 of file rtl_rtl8139_drv.h.

Referenced by dev_rtl8139_open(), rt_rtl8139_close(), rt_rtl8139_hw_start(), rt_rtl8139_rx_interrupt(), and start_up_rtl8139_device().

#define RTL_W16   RTL_W16_F
 

Definition at line 215 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_close(), rt_rtl8139_hw_start(), rt_rtl8139_interrupt(), and rt_rtl8139_mdio_write().

#define RTL_W16_F (  reg,
val16   )     do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
 

Definition at line 200 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_hw_start(), rt_rtl8139_interrupt(), rt_rtl8139_mdio_write(), and rt_rtl8139_rx_interrupt().

#define RTL_W32   RTL_W32_F
 

Definition at line 216 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_close(), rt_rtl8139_hw_start(), rt_rtl8139_send_packet(), and rt_rtl8139_tx_interrupt().

#define RTL_W32_F (  reg,
val32   )     do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
 

Definition at line 201 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_hw_start(), and rt_rtl8139_set_rx_mode().

#define RTL_W8   RTL_W8_F
 

Definition at line 214 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_close(), rt_rtl8139_hw_start(), and start_up_rtl8139_device().

#define RTL_W8_F (  reg,
val8   )     do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
 

Definition at line 199 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_hw_start(), rt_rtl8139_mdio_write(), and start_up_rtl8139_device().

#define RX_BUF_LEN   (8192 << RX_BUF_LEN_IDX)
 

Definition at line 238 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_rx_interrupt().

#define RX_BUF_LEN_IDX   2
 

Definition at line 237 of file rtl_rtl8139_drv.h.

#define RX_BUF_PAD   16
 

Definition at line 239 of file rtl_rtl8139_drv.h.

#define RX_BUF_TOT_LEN   (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
 

Definition at line 241 of file rtl_rtl8139_drv.h.

Referenced by dev_rtl8139_open(), and rt_rtl8139_close().

#define RX_BUF_WRAP_PAD   2048
 

Definition at line 240 of file rtl_rtl8139_drv.h.

#define RX_DMA_BURST   6
 

Definition at line 272 of file rtl_rtl8139_drv.h.

#define RX_FIFO_THRESH   6
 

Definition at line 271 of file rtl_rtl8139_drv.h.

#define RX_RING_SIZE   32
 

Definition at line 306 of file rtl_rtl8139_drv.h.

#define SIGALRM2   RTL_SIGUSR1
 

Definition at line 735 of file rtl_rtl8139_drv.h.

#define TRANSMIT_DEBUG   0
 

Definition at line 732 of file rtl_rtl8139_drv.h.

#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE
 

Definition at line 639 of file rtl_rtl8139_drv.h.

#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE
 

Definition at line 639 of file rtl_rtl8139_drv.h.

#define TX_BUF_SIZE   MAX_ETH_FRAME_SIZE
 

Definition at line 639 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_init_ring().

#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)
 

Definition at line 640 of file rtl_rtl8139_drv.h.

#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)
 

Definition at line 640 of file rtl_rtl8139_drv.h.

#define TX_BUF_TOT_LEN   (TX_BUF_SIZE * NUM_TX_DESC)
 

Definition at line 640 of file rtl_rtl8139_drv.h.

Referenced by dev_rtl8139_open(), and rt_rtl8139_close().

#define TX_DMA_BURST   6
 

Definition at line 273 of file rtl_rtl8139_drv.h.

Referenced by rt_rtl8139_hw_start(), and rt_rtl8139_tx_interrupt().

#define TX_FIFO_THRESH   256
 

Definition at line 644 of file rtl_rtl8139_drv.h.

#define TX_FIFO_THRESH   256
 

Definition at line 644 of file rtl_rtl8139_drv.h.

Referenced by dev_rtl8139_open().

#define TX_RING_SIZE   16
 

Definition at line 305 of file rtl_rtl8139_drv.h.

#define TX_TIMEOUT   (6*HZ)
 

Definition at line 277 of file rtl_rtl8139_drv.h.

Enumeration Type Documentation

anonymous enum
 

Enumeration values:
HAS_MII_XCVR 
HAS_CHIP_XCVR 
HAS_LNK_CHNG 

Definition at line 309 of file rtl_rtl8139_drv.h. 

00309      {
00310         HAS_MII_XCVR = 0x010000,
00311         HAS_CHIP_XCVR = 0x020000,
00312         HAS_LNK_CHNG = 0x040000,
00313 };

enum board_t
 

Enumeration values:
RTL8139 
RTL8139_CB 
SMC1211TX 
DELTA8139 
ADDTRON8139 
DFE538TX 
RTL8129 

Definition at line 322 of file rtl_rtl8139_drv.h. 

00322              {
00323         RTL8139 = 0,
00324         RTL8139_CB,
00325         SMC1211TX,
00326         /*MPX5030,*/
00327         DELTA8139,
00328         ADDTRON8139,
00329         DFE538TX,
00330         RTL8129,
00331 } board_t;

enum Cfg9346Bits
 

Enumeration values:
Cfg9346_Lock 
Cfg9346_Unlock 

Definition at line 582 of file rtl_rtl8139_drv.h. 

00582                  {
00583         Cfg9346_Lock = 0x00,
00584         Cfg9346_Unlock = 0xC0,
00585 };

enum chip_t
 

Enumeration values:
CH_8139 
CH_8139_K 
CH_8139A 
CH_8139B 
CH_8130 
CH_8139C 
CH_8139CP 

Definition at line 295 of file rtl_rtl8139_drv.h. 

00295              {
00296         CH_8139 = 0,
00297         CH_8139_K,
00298         CH_8139A,
00299         CH_8139B,
00300         CH_8130,
00301         CH_8139C,
00302         CH_8139CP,
00303 } chip_t;

enum ChipCmdBits
 

Enumeration values:
CmdReset 
CmdRxEnb 
CmdTxEnb 
RxBufEmpty 

Definition at line 448 of file rtl_rtl8139_drv.h. 

00448                  {
00449         CmdReset = 0x10,
00450         CmdRxEnb = 0x08,
00451         CmdTxEnb = 0x04,
00452         RxBufEmpty = 0x01,
00453 };

enum ClearBitMasks
 

Enumeration values:
MultiIntrClear 
ChipCmdClear 
Config1Clear 

Definition at line 442 of file rtl_rtl8139_drv.h. 

00442                    {
00443         MultiIntrClear = 0xF000,
00444         ChipCmdClear = 0xE2,
00445         Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
00446 };

enum Config1Bits
 

Enumeration values:
Cfg1_PM_Enable 
Cfg1_VPD_Enable 
Cfg1_PIO 
Cfg1_MMIO 
Cfg1_LWAKE 
Cfg1_Driver_Load 
Cfg1_LED0 
Cfg1_LED1 

Definition at line 537 of file rtl_rtl8139_drv.h. 

00537                  {
00538         Cfg1_PM_Enable = 0x01,
00539         Cfg1_VPD_Enable = 0x02,
00540         Cfg1_PIO = 0x04,
00541         Cfg1_MMIO = 0x08,
00542         Cfg1_LWAKE = 0x10,
00543         Cfg1_Driver_Load = 0x20,
00544         Cfg1_LED0 = 0x40,
00545         Cfg1_LED1 = 0x80,
00546 };

enum CPlusCmdBits
 

Enumeration values:
CPlusTxEnb 
CPlusRxEnb 
CPlusCheckSumEnb 

Definition at line 455 of file rtl_rtl8139_drv.h. 

00455                   {
00456         CPlusTxEnb = 0x01,
00457         CPlusRxEnb = 0x02,
00458         CPlusCheckSumEnb = 0x20,
00459 };

enum CPlusRxStatusDesc
 

Enumeration values:
CPlusRxRES 
CPlusRxCRC 
CPlusRxRUNT 
CPlusRxRWT 
CPlusRxFAE 
CPlusRxIPchecksumBIT 
CPlusRxUDPIPchecksumBIT 
CPlusRxTCPIPchecksumBIT 
ProtocolType_NonIP 
ProtocolType_TCPIP 
ProtocolType_UDPIP 
ProtocolType_IP 

Definition at line 461 of file rtl_rtl8139_drv.h. 

00461                        {
00462         CPlusRxRES = 0x00100000,
00463         CPlusRxCRC = 0x00040000,
00464         CPlusRxRUNT= 0x00080000,
00465         CPlusRxRWT = 0x00200000,
00466         CPlusRxFAE = 0x08000000,
00467         CPlusRxIPchecksumBIT  = 0x00008000,
00468         CPlusRxUDPIPchecksumBIT = 0x0000C000,
00469         CPlusRxTCPIPchecksumBIT = 0x0000A000,
00470         ProtocolType_NonIP        = 0,
00471         ProtocolType_TCPIP        = 1,
00472         ProtocolType_UDPIP        = 2,
00473         ProtocolType_IP           = 3,
00474 };

enum CPlusTxChecksumOffload
 

Enumeration values:
CPlusTxIPchecksumOffload 
CPlusTxUDPchecksumOffload 
CPlusTxTCPchecksumOffload 

Definition at line 476 of file rtl_rtl8139_drv.h. 

00476                             {
00477         CPlusTxIPchecksumOffload  = 0x00040000,
00478         CPlusTxUDPchecksumOffload = 0x00020000,
00479         CPlusTxTCPchecksumOffload = 0x00010000,
00480 };

enum CSCRBits
 

Enumeration values:
CSCR_LinkOKBit 
CSCR_LinkChangeBit 
CSCR_LinkStatusBits 
CSCR_LinkDownOffCmd 
CSCR_LinkDownCmd 

Definition at line 573 of file rtl_rtl8139_drv.h. 

00573               {
00574         CSCR_LinkOKBit = 0x0400,
00575         CSCR_LinkChangeBit = 0x0800,
00576         CSCR_LinkStatusBits = 0x0f000,
00577         CSCR_LinkDownOffCmd = 0x003c0,
00578         CSCR_LinkDownCmd = 0x0f3c0,
00579 };

enum IntrStatusBits
 

Enumeration values:
PCIErr 
PCSTimeout 
RxFIFOOver 
RxUnderrun 
RxOverflow 
TxErr 
TxOK 
RxErr 
RxOK 

Definition at line 483 of file rtl_rtl8139_drv.h. 

00483                     {
00484         PCIErr = 0x8000,
00485         PCSTimeout = 0x4000,
00486         RxFIFOOver = 0x40,
00487         RxUnderrun = 0x20,
00488         RxOverflow = 0x10,
00489         TxErr = 0x08,
00490         TxOK = 0x04,
00491         RxErr = 0x02,
00492         RxOK = 0x01,
00493 };

enum MediaStatusBits
 

Enumeration values:
DuplexMode 
Speed_10 

Definition at line 597 of file rtl_rtl8139_drv.h. 

00597                      {
00598         DuplexMode = 0x0100,    //in BasicModeControlRegister
00599         Speed_10 = 0x08,                //in Media Status Register
00600 };

enum NegotiationBits
 

Enumeration values:
AutoNegotiationEnable 
AutoNegotiationRestart 
AutoNegoAbility10half 
AutoNegoAbility10full 
AutoNegoAbility100half 
AutoNegoAbility100full 

Definition at line 588 of file rtl_rtl8139_drv.h. 

00588                      {
00589         AutoNegotiationEnable  = 0x1000,
00590         AutoNegotiationRestart = 0x0200,
00591         AutoNegoAbility10half  = 0x21,
00592         AutoNegoAbility10full  = 0x41,
00593         AutoNegoAbility100half  = 0x81,
00594         AutoNegoAbility100full  = 0x101,
00595 };

enum RTL8139_registers
 

Enumeration values:
MAC0 
MAR0 
TxStatus0 
TxAddr0 
RxBuf 
RxEarlyCnt 
RxEarlyStatus 
ChipCmd 
RxBufPtr 
RxBufAddr 
IntrMask 
IntrStatus 
TxConfig 
ChipVersion 
RxConfig 
Timer 
RxMissed 
Cfg9346 
Config0 
Config1 
FlashReg 
MediaStatus 
Config3 
Config4 
HltClk 
MultiIntr 
TxSummary 
BasicModeCtrl 
BasicModeStatus 
NWayAdvert 
NWayLPAR 
NWayExpansion 
FIFOTMS 
CSCR 
PARA78 
PARA7c 
Config5 
CPlusTxPoll 
CPlusCmd 
CPlusRxStartAddr 
CPlusTxStartAddr 
CPlusEarlyTxThldReg 

Definition at line 397 of file rtl_rtl8139_drv.h. 

00397                        {
00398         MAC0 = 0,               /* Ethernet hardware address. */
00399         MAR0 = 8,               /* Multicast filter. */
00400         TxStatus0 = 0x10,       /* Transmit status (Four 32bit registers). */
00401         TxAddr0 = 0x20,         /* Tx descriptors (also four 32bit). */
00402         RxBuf = 0x30,
00403         RxEarlyCnt = 0x34,
00404         RxEarlyStatus = 0x36,
00405         ChipCmd = 0x37,
00406         RxBufPtr = 0x38,
00407         RxBufAddr = 0x3A,
00408         IntrMask = 0x3C,
00409         IntrStatus = 0x3E,
00410         TxConfig = 0x40,
00411         ChipVersion = 0x43,
00412         RxConfig = 0x44,
00413         Timer = 0x48,           /* A general-purpose counter. */
00414         RxMissed = 0x4C,        /* 24 bits valid, write clears. */
00415         Cfg9346 = 0x50,
00416         Config0 = 0x51,
00417         Config1 = 0x52,
00418         FlashReg = 0x54,
00419         MediaStatus = 0x58,
00420         Config3 = 0x59,
00421         Config4 = 0x5A,         /* absent on RTL-8139A */
00422         HltClk = 0x5B,
00423         MultiIntr = 0x5C,
00424         TxSummary = 0x60,
00425         BasicModeCtrl = 0x62,
00426         BasicModeStatus = 0x64,
00427         NWayAdvert = 0x66,
00428         NWayLPAR = 0x68,
00429         NWayExpansion = 0x6A,
00430         /* Undocumented registers, but required for proper operation. */
00431         FIFOTMS = 0x70,         /* FIFO Control and test. */
00432         CSCR = 0x74,            /* Chip Status and Configuration Register. */
00433         PARA78 = 0x78,
00434         PARA7c = 0x7c,          /* Magic transceiver parameter register. */
00435         Config5 = 0xD8,         /* absent on RTL-8139A */
00436 //  For C+ Registers
00437         CPlusTxPoll=0xD9, CPlusCmd=0xE0, CPlusRxStartAddr=0xE4,
00438         CPlusTxStartAddr=0x20, CPlusEarlyTxThldReg=0xEC,
00439 };

enum rx_mode_bits
 

Enumeration values:
AcceptErr 
AcceptRunt 
AcceptBroadcast 
AcceptMulticast 
AcceptMyPhys 
AcceptAllPhys 

Definition at line 515 of file rtl_rtl8139_drv.h. 

00515                   {
00516         AcceptErr = 0x20,
00517         AcceptRunt = 0x10,
00518         AcceptBroadcast = 0x08,
00519         AcceptMulticast = 0x04,
00520         AcceptMyPhys = 0x02,
00521         AcceptAllPhys = 0x01,
00522 };

enum RxConfigBits
 

Enumeration values:
RxCfgEarlyRxNone 
RxCfgEarlyRxShift 
RxCfgFIFOShift 
RxCfgFIFONone 
RxCfgDMAShift 
RxCfgDMAUnlimited 
RxCfgRcv8K 
RxCfgRcv16K 
RxCfgRcv32K 
RxCfgRcv64K 
RxNoWrap 

Definition at line 548 of file rtl_rtl8139_drv.h. 

00548                   {
00549         /* Early Rx threshold, none or X/16 */
00550         RxCfgEarlyRxNone = 0,
00551         RxCfgEarlyRxShift = 24,
00552  
00553         /* rx fifo threshold */
00554         RxCfgFIFOShift = 13,
00555         RxCfgFIFONone = (7 << RxCfgFIFOShift),
00556  
00557         /* Max DMA burst */
00558         RxCfgDMAShift = 8,
00559         RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
00560  
00561         /* rx ring buffer length */
00562         RxCfgRcv8K = 0,
00563         RxCfgRcv16K = (1 << 11),
00564         RxCfgRcv32K = (1 << 12),
00565         RxCfgRcv64K = (1 << 11) | (1 << 12),
00566  
00567         /* Disable packet wrap at end of Rx buffer */
00568         RxNoWrap = (1 << 7),
00569 };

enum RxStatusBits
 

Enumeration values:
RxMulticast 
RxPhysical 
RxBroadcast 
RxBadSymbol 
RxRunt 
RxTooLong 
RxCRCErr 
RxBadAlign 
RxStatusOK 

Definition at line 502 of file rtl_rtl8139_drv.h. 

00502                   {
00503         RxMulticast = 0x8000,
00504         RxPhysical = 0x4000,
00505         RxBroadcast = 0x2000,
00506         RxBadSymbol = 0x0020,
00507         RxRunt = 0x0010,
00508         RxTooLong = 0x0008,
00509         RxCRCErr = 0x0004,
00510         RxBadAlign = 0x0002,
00511         RxStatusOK = 0x0001,
00512 };

enum tx_config_bits
 

Enumeration values:
TxIFG1 
TxIFG0 
TxLoopBack 
TxCRC 
TxClearAbt 
TxDMAShift 
TxVersionMask 

Definition at line 525 of file rtl_rtl8139_drv.h. 

00525                     {
00526         TxIFG1 = (1 << 25),     /* Interframe Gap Time */
00527         TxIFG0 = (1 << 24),     /* Enabling these bits violates IEEE 802.3 */
00528         TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
00529         TxCRC = (1 << 16),      /* DISABLE appending CRC to end of Tx packets */
00530         TxClearAbt = (1 << 0),  /* Clear abort (WO) */
00531         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
00532  
00533         TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
00534 };

enum TxStatusBits
 

Enumeration values:
TxHostOwns 
TxUnderrun 
TxStatOK 
TxOutOfWindow 
TxAborted 
TxCarrierLost 

Definition at line 494 of file rtl_rtl8139_drv.h. 

00494                   {
00495         TxHostOwns = 0x2000,
00496         TxUnderrun = 0x4000,
00497         TxStatOK = 0x8000,
00498         TxOutOfWindow = 0x20000000,
00499         TxAborted = 0x40000000,
00500         TxCarrierLost = 0x80000000,
00501 };

Variable Documentation

struct { ... } __devinitdata[] [static]
 

int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1} [static]
 

Definition at line 606 of file rtl_rtl8139_drv.h.

u32 hw_flags
 

Definition at line 337 of file rtl_rtl8139_drv.h.

int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1} [static]
 

Definition at line 605 of file rtl_rtl8139_drv.h.

char mii_2_8139_map[8] [static]
 

Initial value:

 {
        BasicModeCtrl,
        BasicModeStatus,
        0,
        0,
        NWayAdvert,
        NWayLPAR,
        NWayExpansion,
        0
}

Definition at line 625 of file rtl_rtl8139_drv.h.

const char* name
 

Definition at line 353 of file rtl_rtl8139_drv.h.

const u16 rtl8139_intr_mask [static]
 

Initial value:

        PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
        TxErr | TxOK | RxErr | RxOK

Definition at line 646 of file rtl_rtl8139_drv.h.

const unsigned int rtl8139_rx_config [static]
 

Initial value:

          RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
          (RX_FIFO_THRESH << RxCfgFIFOShift) |
          (RX_DMA_BURST << RxCfgDMAShift)

Definition at line 650 of file rtl_rtl8139_drv.h.

const { ... } rtl_chip_info[] [static]
 

struct rx_buffer_t rx_buffer
 

Referenced by FIFO_add_frame_to_buffer(), FIFO_dealloc_rx_buffer(), FIFO_extract_frame_of_buffer(), and FIFO_initialize_rx_buffer().

u32 RxConfigMask
 

Definition at line 355 of file rtl_rtl8139_drv.h.

u8 version
 

Definition at line 354 of file rtl_rtl8139_drv.h.

Generated on Wed Jan 14 12:59:11 2004 for RTL-lwIP-0.4 by doxygen 1.3.4