rtl_rtl8139_drv.h

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/*
 
        8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
 
        Maintained by Jeff Garzik <jgarzik@mandrakesoft.com>
        Copyright 2000,2001 Jeff Garzik
 
        Much code comes from Donald Becker's rtl8139.c driver,
        versions 1.13 and older.  This driver was originally based
        on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:
 
        -----<snip>-----
 
                Written 1997-2001 by Donald Becker.
                This software may be used and distributed according to the
                terms of the GNU General Public License (GPL), incorporated
                herein by reference.  Drivers based on or derived from this
                code fall under the GPL and must retain the authorship,
                copyright and license notice.  This file is not a complete
                program and may only be used when the entire operating
                system is licensed under the GPL.
 
                This driver is for boards based on the RTL8129 and RTL8139
                PCI ethernet chips.
 
                The author may be reached as becker@scyld.com, or C/O Scyld
                Computing Corporation 410 Severn Ave., Suite 210 Annapolis
                MD 21403

                Support and updates available at
                http://www.scyld.com/network/rtl8139.html
 
                Twister-tuning table provided by Kinston
                <shangh@realtek.com.tw>.
 
        -----<snip>-----
        This software may be used and distributed according to the terms
        of the GNU General Public License, incorporated herein by reference.
 
        Contributors:
 
                Donald Becker - he wrote the original driver, kudos to him!
                (but please don't e-mail him for support, this isn't his driver)
 
                Tigran Aivazian - bug fixes, skbuff free cleanup
 
                Martin Mares - suggestions for PCI cleanup
 
                David S. Miller - PCI DMA and softnet updates
 
                Ernst Gill - fixes ported from BSD driver
 
                Daniel Kobras - identified specific locations of
                        posted MMIO write bugginess
 
                Gerard Sharp - bug fix, testing and feedback

                David Ford - Rx ring wrap fix

                Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
                to find and fix a crucial bug on older chipsets.
 
                Donald Becker/Chris Butterworth/Marcus Westergren -
                Noticed various Rx packet size-related buglets.
 
                Santiago Garcia Mantinan - testing and feedback
 
                Jens David - 2.2.x kernel backports
 
                Martin Dennett - incredibly helpful insight on undocumented
                features of the 8139 chips
 
                Jean-Jacques Michel - bug fix
 
                Tobias Ringström - Rx interrupt status checking suggestion
 
                Andrew Morton - Clear blocked signals, avoid
                buffer overrun setting current->comm.
 
        Submitting bug reports:
 
                "rtl8139-diag -mmmaaavvveefN" output
                enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
 
                See 8139too.txt for more details.

-----------------------------------------------------------------------------
2001/09/21
Comments by ShuChen Shao
 
1.This driver is originally based on 8139too.c version "0.9.15".
 
2.It has been enhanced to support RTL8139C+ PCI ethernet chips and tested in 2.4.2 kernel.
 
3.RTL8139C+ PCI ethernet chips is set to support C+ mode by default.
  If FORCE_C_Mode below is enable, the RTL8139C+ chip will be forced to support C mode
  after reboot.
 
4.This program can be compiled at /usr/src/linux-2.4.2/drivers/net/ using the attached Makefile.
  And the object file named 8139too.o should be moved to the directory
  /lib/modules/2.4.2-2/kernel/drivers/net/

-----------------------------------------------------------------------------




=====================================================================================
                          PORTING TO RT-LINUX
=====================================================================================
 
15 May 2003
ByungGi Baek <gi@realtimewave.com||weapon100@empal.com>
 
1. This driver is originally based on 8139too.c
 
2. This file is also based in one file part of the RTL-lwIP TCP/IP stack.
   The file is: rt_3c905x_phys.c which author is:
   Sergio Perez Alcañiz <serpeal@disca.upv.es>
 
3. This file is compiled and tested on RTL-lwIP-0.2.1
 
4. Unload the original 8139 linux driver then load this driver.
 
 
=====================================================================================
 
*/




#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/in.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/mii.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/highmem.h>
#include <asm/irq.h>                    /* For NR_IRQS only. */
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/uaccess.h>


#include <rtl_sched.h>
#include <signal.h>
#include <time.h>
 
#define DRV_NAME        "rtl8139"
#define DRV_VERSION     "0.1"
#define DRV_RELDATE     " 4 2003"

#undef USE_IO_OPS

#ifdef USE_IO_OPS 

#define RTL_R8(reg)             inb (((unsigned long)ioaddr) + (reg))
#define RTL_R16(reg)            inw (((unsigned long)ioaddr) + (reg))
#define RTL_R32(reg)            ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
#define RTL_W8(reg, val8)       outb ((val8), ((unsigned long)ioaddr) + (reg))
#define RTL_W16(reg, val16)     outw ((val16), ((unsigned long)ioaddr) + (reg))
#define RTL_W32(reg, val32)     outl ((val32), ((unsigned long)ioaddr) + (reg))
#define RTL_W8_F                RTL_W8
#define RTL_W16_F               RTL_W16
#define RTL_W32_F               RTL_W32
#undef readb
#undef readw
#undef readl
#undef writeb
#undef writew
#undef writel
#define readb(addr) inb((unsigned long)(addr))
#define readw(addr) inw((unsigned long)(addr))
#define readl(addr) inl((unsigned long)(addr))
#define writeb(val,addr) outb((val),(unsigned long)(addr))
#define writew(val,addr) outw((val),(unsigned long)(addr))
#define writel(val,addr) outl((val),(unsigned long)(addr))

#else 

/* write MMIO register, with flush */
/* Flush avoids rtl8139 bug w/ posted MMIO writes */
#define RTL_W8_F(reg, val8)     do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
#define RTL_W16_F(reg, val16)   do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
#define RTL_W32_F(reg, val32)   do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
 
 
#if MMIO_FLUSH_AUDIT_COMPLETE
 
/* write MMIO register */
#define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 
#else
 
/* write MMIO register, then flush */
#define RTL_W8          RTL_W8_F
#define RTL_W16         RTL_W16_F
#define RTL_W32         RTL_W32_F
 
#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
 
/* read MMIO register */
#define RTL_R8(reg)             readb (ioaddr + (reg))
#define RTL_R16(reg)            readw (ioaddr + (reg))
#define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 
#endif /* USE_IO_OPS */



 
#define MAX_THREADS 10
 
#define RTL8139_VENDOR_ID 0x10EC
#define RTL8139_DEVICE_ID 0X8139

#define PKT_BUF_SZ      1536    /* Size of each temporary Rx buffer.*/
/* Size of the in-memory receive ring. */
#define RX_BUF_LEN_IDX  2       /* 0==8K, 1==16K, 2==32K, 3==64K */
#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
#define RX_BUF_PAD 16
#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

#define MAX_ADDR_LEN    8               /* Largest hardware address length */                               

 
/* Number of Tx descriptor registers. */
#define NUM_TX_DESC     4
 
/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
#define MAX_ETH_FRAME_SIZE      1536
 
/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
#define TX_BUF_SIZE     MAX_ETH_FRAME_SIZE
#define TX_BUF_TOT_LEN  (TX_BUF_SIZE * NUM_TX_DESC)

/* Number of Tx descriptor registers. */
#define NUM_TX_DESC     4
 
/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
#define MAX_ETH_FRAME_SIZE      1536
 
/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
#define TX_BUF_SIZE     MAX_ETH_FRAME_SIZE
#define TX_BUF_TOT_LEN  (TX_BUF_SIZE * NUM_TX_DESC)
 
/* PCI Tuning Parameters
   Threshold is bytes transferred to chip before transmission starts. */
#define TX_FIFO_THRESH 256      /* In bytes, rounded down to 32 byte units. */
 
/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
#define RX_FIFO_THRESH  6       /* Rx buffer level before first PCI xfer.  */
#define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
#define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 
/* Operational parameters that usually are not changed. */
/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT  (6*HZ)





/* for 8139C+ only */
#define NUM_CP_TX_DESC  64                      /* Number of Tx descriptor registers for C+*/
#define NUM_CP_RX_DESC  64                      /* Number of Rx descriptor registers for C+*/
#define CP_RX_BUF_SIZE  2000



struct ring_info {
        struct sk_buff *skb;
        dma_addr_t mapping;
};
 
typedef enum {
        CH_8139 = 0,
        CH_8139_K,
        CH_8139A,
        CH_8139B,
        CH_8130,
        CH_8139C,
        CH_8139CP,
} chip_t; 

#define TX_RING_SIZE    16
#define RX_RING_SIZE    32


enum {
        HAS_MII_XCVR = 0x010000,
        HAS_CHIP_XCVR = 0x020000,
        HAS_LNK_CHNG = 0x040000,
};
 
#define RTL_MIN_IO_SIZE 0x80
#define RTL8139B_IO_SIZE 256
 
#define RTL8129_CAPS    HAS_MII_XCVR
#define RTL8139_CAPS    HAS_CHIP_XCVR|HAS_LNK_CHNG
 
 
typedef enum {
        RTL8139 = 0,
        RTL8139_CB,
        SMC1211TX,
        /*MPX5030,*/
        DELTA8139,
        ADDTRON8139,
        DFE538TX,
        RTL8129,
} board_t;


/* indexed by board_t, above */
static struct {
        const char *name;
        u32 hw_flags;
} board_info[] __devinitdata = {
        { "RealTek RTL8139CP Fast Ethernet", RTL8139_CAPS },
        { "RealTek RTL8139B PCI/CardBus", RTL8139_CAPS },
        { "SMC1211TX EZCard 10/100 (RealTek RTL8139)", RTL8139_CAPS },
/*      { MPX5030, "Accton MPX5030 (RealTek RTL8139)", RTL8139_CAPS },*/
        { "Delta Electronics 8139 10/100BaseTX", RTL8139_CAPS },
        { "Addtron Technolgy 8139 10/100BaseTX", RTL8139_CAPS },
        { "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },
        { "RealTek RTL8129", RTL8129_CAPS },
};



/* directly indexed by chip_t, above */
const static struct {
        const char *name;
        u8 version; /* from RTL8139C docs */
        u32 RxConfigMask; /* should clear the bits supported by this chip */
} rtl_chip_info[] = {
        { "RTL-8139",
          0x40,
          0xf0fe0040, /* XXX copied from RTL8139A, verify */
        },
 
        { "RTL-8139 rev K",
          0x60,
          0xf0fe0040,
        },
 
        { "RTL-8139A",
          0x70,
          0xf0fe0040,
        },
 
        { "RTL-8139B",
          0x78,
          0xf0fc0040
        },
 
        { "RTL-8130",
          0x7C,
          0xf0fe0040, /* XXX copied from RTL8139A, verify */
        },
 
        { "RTL-8139C",
          0x74,
          0xf0fc0040, /* XXX copied from RTL8139B, verify */
        },
 
        { "RTL-8139CP",
          0x76,
          0xf0fc0040, /* XXX copied from RTL8139B, verify */
        },
};


/* The rest of these values should never change. */
 
/* Symbolic offsets to registers. */
enum RTL8139_registers {
        MAC0 = 0,               /* Ethernet hardware address. */
        MAR0 = 8,               /* Multicast filter. */
        TxStatus0 = 0x10,       /* Transmit status (Four 32bit registers). */
        TxAddr0 = 0x20,         /* Tx descriptors (also four 32bit). */
        RxBuf = 0x30,
        RxEarlyCnt = 0x34,
        RxEarlyStatus = 0x36,
        ChipCmd = 0x37,
        RxBufPtr = 0x38,
        RxBufAddr = 0x3A,
        IntrMask = 0x3C,
        IntrStatus = 0x3E,
        TxConfig = 0x40,
        ChipVersion = 0x43,
        RxConfig = 0x44,
        Timer = 0x48,           /* A general-purpose counter. */
        RxMissed = 0x4C,        /* 24 bits valid, write clears. */
        Cfg9346 = 0x50,
        Config0 = 0x51,
        Config1 = 0x52,
        FlashReg = 0x54,
        MediaStatus = 0x58,
        Config3 = 0x59,
        Config4 = 0x5A,         /* absent on RTL-8139A */
        HltClk = 0x5B,
        MultiIntr = 0x5C,
        TxSummary = 0x60,
        BasicModeCtrl = 0x62,
        BasicModeStatus = 0x64,
        NWayAdvert = 0x66,
        NWayLPAR = 0x68,
        NWayExpansion = 0x6A,
        /* Undocumented registers, but required for proper operation. */
        FIFOTMS = 0x70,         /* FIFO Control and test. */
        CSCR = 0x74,            /* Chip Status and Configuration Register. */
        PARA78 = 0x78,
        PARA7c = 0x7c,          /* Magic transceiver parameter register. */
        Config5 = 0xD8,         /* absent on RTL-8139A */
//  For C+ Registers
        CPlusTxPoll=0xD9, CPlusCmd=0xE0, CPlusRxStartAddr=0xE4,
        CPlusTxStartAddr=0x20, CPlusEarlyTxThldReg=0xEC,
};


enum ClearBitMasks {
        MultiIntrClear = 0xF000,
        ChipCmdClear = 0xE2,
        Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
};
 
enum ChipCmdBits {
        CmdReset = 0x10,
        CmdRxEnb = 0x08,
        CmdTxEnb = 0x04,
        RxBufEmpty = 0x01,
};
 
enum CPlusCmdBits {
        CPlusTxEnb = 0x01,
        CPlusRxEnb = 0x02,
        CPlusCheckSumEnb = 0x20,
};

enum CPlusRxStatusDesc {
        CPlusRxRES = 0x00100000,
        CPlusRxCRC = 0x00040000,
        CPlusRxRUNT= 0x00080000,
        CPlusRxRWT = 0x00200000,
        CPlusRxFAE = 0x08000000,
        CPlusRxIPchecksumBIT  = 0x00008000,
        CPlusRxUDPIPchecksumBIT = 0x0000C000,
        CPlusRxTCPIPchecksumBIT = 0x0000A000,
        ProtocolType_NonIP        = 0,
        ProtocolType_TCPIP        = 1,
        ProtocolType_UDPIP        = 2,
        ProtocolType_IP           = 3,
};
 
enum CPlusTxChecksumOffload {
        CPlusTxIPchecksumOffload  = 0x00040000,
        CPlusTxUDPchecksumOffload = 0x00020000,
        CPlusTxTCPchecksumOffload = 0x00010000,
};

/* Interrupt register bits, using my own meaningful names. */
enum IntrStatusBits {
        PCIErr = 0x8000,
        PCSTimeout = 0x4000,
        RxFIFOOver = 0x40,
        RxUnderrun = 0x20,
        RxOverflow = 0x10,
        TxErr = 0x08,
        TxOK = 0x04,
        RxErr = 0x02,
        RxOK = 0x01,
};
enum TxStatusBits {
        TxHostOwns = 0x2000,
        TxUnderrun = 0x4000,
        TxStatOK = 0x8000,
        TxOutOfWindow = 0x20000000,
        TxAborted = 0x40000000,
        TxCarrierLost = 0x80000000,
};
enum RxStatusBits {
        RxMulticast = 0x8000,
        RxPhysical = 0x4000,
        RxBroadcast = 0x2000,
        RxBadSymbol = 0x0020,
        RxRunt = 0x0010,
        RxTooLong = 0x0008,
        RxCRCErr = 0x0004,
        RxBadAlign = 0x0002,
        RxStatusOK = 0x0001,
};

/* Bits in RxConfig. */
enum rx_mode_bits {
        AcceptErr = 0x20,
        AcceptRunt = 0x10,
        AcceptBroadcast = 0x08,
        AcceptMulticast = 0x04,
        AcceptMyPhys = 0x02,
        AcceptAllPhys = 0x01,
};
 
/* Bits in TxConfig. */
enum tx_config_bits {
        TxIFG1 = (1 << 25),     /* Interframe Gap Time */
        TxIFG0 = (1 << 24),     /* Enabling these bits violates IEEE 802.3 */
        TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
        TxCRC = (1 << 16),      /* DISABLE appending CRC to end of Tx packets */
        TxClearAbt = (1 << 0),  /* Clear abort (WO) */
        TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 
        TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
};

/* Bits in Config1 */
enum Config1Bits {
        Cfg1_PM_Enable = 0x01,
        Cfg1_VPD_Enable = 0x02,
        Cfg1_PIO = 0x04,
        Cfg1_MMIO = 0x08,
        Cfg1_LWAKE = 0x10,
        Cfg1_Driver_Load = 0x20,
        Cfg1_LED0 = 0x40,
        Cfg1_LED1 = 0x80,
};

enum RxConfigBits {
        /* Early Rx threshold, none or X/16 */
        RxCfgEarlyRxNone = 0,
        RxCfgEarlyRxShift = 24,
 
        /* rx fifo threshold */
        RxCfgFIFOShift = 13,
        RxCfgFIFONone = (7 << RxCfgFIFOShift),
 
        /* Max DMA burst */
        RxCfgDMAShift = 8,
        RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
 
        /* rx ring buffer length */
        RxCfgRcv8K = 0,
        RxCfgRcv16K = (1 << 11),
        RxCfgRcv32K = (1 << 12),
        RxCfgRcv64K = (1 << 11) | (1 << 12),
 
        /* Disable packet wrap at end of Rx buffer */
        RxNoWrap = (1 << 7),
};

/* Twister tuning parameters from RealTek.
   Completely undocumented, but required to tune bad links. */
enum CSCRBits {
        CSCR_LinkOKBit = 0x0400,
        CSCR_LinkChangeBit = 0x0800,
        CSCR_LinkStatusBits = 0x0f000,
        CSCR_LinkDownOffCmd = 0x003c0,
        CSCR_LinkDownCmd = 0x0f3c0,
};
 
 
enum Cfg9346Bits {
        Cfg9346_Lock = 0x00,
        Cfg9346_Unlock = 0xC0,
};
 
 
enum NegotiationBits {
        AutoNegotiationEnable  = 0x1000,
        AutoNegotiationRestart = 0x0200,
        AutoNegoAbility10half  = 0x21,
        AutoNegoAbility10full  = 0x41,
        AutoNegoAbility100half  = 0x81,
        AutoNegoAbility100full  = 0x101,
};
 
enum MediaStatusBits {
        DuplexMode = 0x0100,    //in BasicModeControlRegister
        Speed_10 = 0x08,                //in Media Status Register
};

/* A few user-configurable values. */
/* media options */
#define MAX_UNITS 8
static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
 
/* MII serial management: mostly bogus for now. */
/* Read and write the MII management registers using software-generated
   serial MDIO protocol.
   The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
   "overclocking" issues. */
#define MDIO_DIR                0x80
#define MDIO_DATA_OUT   0x04
#define MDIO_DATA_IN    0x02
#define MDIO_CLK                0x01
#define MDIO_WRITE0 (MDIO_DIR)
#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
 
#define rt_rtl8139_mdio_delay(mdio_addr)   readb(mdio_addr)
#define mdio_delay(mdio_addr)   readb(mdio_addr)
 
 
static char mii_2_8139_map[8] = {
        BasicModeCtrl,
        BasicModeStatus,
        0,
        0,
        NWayAdvert,
        NWayLPAR,
        NWayExpansion,
        0
};


 
/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
#define TX_BUF_SIZE     MAX_ETH_FRAME_SIZE
#define TX_BUF_TOT_LEN  (TX_BUF_SIZE * NUM_TX_DESC)
 
/* PCI Tuning Parameters
   Threshold is bytes transferred to chip before transmission starts. */
#define TX_FIFO_THRESH 256      /* In bytes, rounded down to 32 byte units. */

static const u16 rtl8139_intr_mask =
        PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
        TxErr | TxOK | RxErr | RxOK;
 
static const unsigned int rtl8139_rx_config =
          RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
          (RX_FIFO_THRESH << RxCfgFIFOShift) |
          (RX_DMA_BURST << RxCfgDMAShift);


/********************************************************************** */
 
struct rtl8139_private {
        void *mmio_addr;
        unsigned int mmio_len;
        int drv_flags;
        struct pci_dev *pci_dev;
        struct net_device_stats stats;
        unsigned char *rx_ring;
        unsigned int cur_rx;    /* Index into the Rx buffer of next Rx pkt. */
        unsigned int tx_flag;
        unsigned long cur_tx;
        unsigned long dirty_tx;
        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
        struct ring_info tx_info[NUM_TX_DESC];
        unsigned char *tx_buf[NUM_TX_DESC];     /* Tx bounce buffers */
        unsigned char *tx_bufs; /* Tx bounce buffer region. */
        dma_addr_t rx_ring_dma;
        dma_addr_t tx_bufs_dma;
        signed char phys[4];            /* MII device addresses. */
        u16 advertising;                /* NWay media advertisement */
        char twistie, twist_row, twist_col;     /* Twister tune state. */
        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
        unsigned int duplex_lock:1;
        unsigned int default_port:4;    /* Last dev->if_port value. */
        unsigned int media2:4;  /* Secondary monitored media port. */
        unsigned int medialock:1;       /* Don't sense media type. */
        unsigned int mediasense:1;      /* Media sensing in progress. */
        spinlock_t lock;
        chip_t chipset;
        pid_t thr_pid;
        wait_queue_head_t thr_wait;
 
#if LINUX_VERSION_CODE < 0x20407
        struct semaphore thr_exited;
#else
        struct completion thr_exited;
#endif
 
 
  // For 8139C+
        int AutoNegoAbility;
        unsigned long CP_cur_tx;
        unsigned long CP_dirty_tx;
        unsigned long CP_cur_rx;
        unsigned char *TxDescArrays;
        unsigned char *RxDescArrays;
        struct CPlusTxDesc *TxDescArray;
        struct CPlusRxDesc *RxDescArray;
        unsigned char *RxBufferRings;
        unsigned char *RxBufferRing[NUM_CP_RX_DESC];
        struct sk_buff* Tx_skbuff[NUM_CP_TX_DESC];
/* For lwIP in RTLinux */
  int mtu;
  unsigned char dev_addr[MAX_ADDR_LEN]; /* hw address   */
  long ioaddr;
  unsigned long rx_packets;
  unsigned long rx_frames_for_us;
  unsigned char if_port;
  int must_free_irq;
  int must_free_region;
  unsigned char *rx_skbuff[RX_RING_SIZE];
  unsigned char *tx_skbuff[TX_RING_SIZE];


};


#define PCI_DEBUG 0
#define EEPROM_CONTENTS_DEBUG 0
#define MAC_ADDRESS_DEBUG 0
#define FUNCTION_CALL_DEBUG 0
#define INITIALIZATION_DEBUG 0
#define RECEIVE_DEBUG 0
#define PACKET_DATA_DEBUG 0
#define INTERRUPT_DEBUG 0
#define TRANSMIT_DEBUG 0
#define ERROR_DEBUG 1
 
#define SIGALRM2 RTL_SIGUSR1
 
#define DEBUG(x,y) if(x) printk y

#include <rtl_sync.h>
#include <rtl_core.h>
#include <rtl_printf.h>
#include <time.h>
#include <asm/io.h>
#include <rtl_posixio.h>
#include <sys/mman.h>
#include <errno.h>
#include <unistd.h>
#include <rtl.h>
#include <rtl_malloc.h>
#include <rtl_sema.h>
#include <rtl_sync.h>
#include "memcopy.h"

 
#define MAX_RX_BUFFER_ENTRIES 50

struct rx_buffer_t{
  struct rx_slot_t *first;
  struct rx_slot_t *add;
  struct rx_slot_t *extract;
}rx_buffer;



struct rx_slot_t{
  struct rx_slot_t *next;
  unsigned int length;
  unsigned char *data;
  unsigned char read;
#ifdef TIME_DEBUG
  struct timeval begin;
  struct timeval end;
#endif
};

---