RTL-lwIP-0.4: rtl_3c905cx_drv.h File Reference

00624                                                      {
00625   struct vortex_chip_info * const vci = &vortex_info;
00626   unsigned int eeprom[0x40], checksum = 0;              /* EEPROM contents */
00627   char *print_name;
00628   int retval;
00629   long ioaddr;
00630   int i,step;
00631 
00632   print_name = dev ? dev->slot_name : "3c59x";
00633 
00634   ioaddr = rt_pci_resource_start(dev, 0);
00635 
00636   rt_3c905c_vp.drv_flags = vci->drv_flags;
00637   rt_3c905c_vp.has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
00638   rt_3c905c_vp.io_size = vci->io_size;
00639   rt_3c905c_vp.card_idx = 0;
00640   rt_3c905c_vp.ioaddr = ioaddr;
00641   rt_3c905c_vp.media_override = 7;
00642   rt_3c905c_vp.mtu = mtu;
00643 
00644   print_name = dev ? dev->slot_name : "3c59x";
00645 
00646   /* PCI-only startup logic */
00647   if (dev) {
00648     if (request_region(ioaddr, vci->io_size, print_name) != NULL){
00649       rt_3c905c_vp.must_free_region = 1;
00650      }
00651 
00652     /* enable bus-mastering if necessary */             
00653     if (vci->flags & PCI_USES_MASTER)
00654       pci_set_master (dev);
00655 
00656     rt_3c905c_vp.pdev = dev;
00657 
00658     /* Makes sure rings are at least 16 byte aligned. */
00659     rt_3c905c_vp.rx_ring = pci_alloc_consistent(dev, sizeof(struct boom_rx_desc) * RX_RING_SIZE, &rt_3c905c_vp.rx_ring_dma);
00660     rt_3c905c_vp.tx_ring = pci_alloc_consistent(dev, sizeof(struct boom_tx_desc) * TX_RING_SIZE, &rt_3c905c_vp.tx_ring_dma);
00661 
00662     retval = -ENOMEM;
00663     if ((rt_3c905c_vp.rx_ring == 0) || (rt_3c905c_vp.tx_ring == 0))
00664       goto free_region;
00665         
00666     EL3WINDOW(0);
00667     {
00668       int base;
00669 
00670       if (vci->drv_flags & EEPROM_8BIT)
00671         base = 0x230;
00672       else if (vci->drv_flags & EEPROM_OFFSET)
00673         base = EEPROM_Read + 0x30;
00674       else
00675         base = EEPROM_Read;
00676 
00677       for (i = 0; i < 0x40; i++) {
00678         int timer;
00679         
00680         /* This means that we want to read EepromCommand Register and disable writting */
00681         /* Issuing ReadRegister & WriteDisable                                         */
00682         outw(base + i, ioaddr + Wn0EepromCmd);
00683 
00684         for (timer = 10; timer >= 0; timer--) {
00685 
00686           /* The read data is available through the EepromData register 162us after  */
00687           /* the ReadRegister command has been issued                                */
00688           rtl_delay(162000);
00689 
00690           /* Bit 15th (eepromBusy) of EepromCommand register is a read-only bit asserted   */
00691           /* during the execution of EEProm commands. Further commans should not be issued */
00692           /* to the EepromCommand register, nor should data be read from the EepromData    */
00693           /* register while this bit is true                                               */
00694           if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
00695             break;
00696         }
00697 
00698         /* Save the contents of the 3C90xC NIC's EEPROM     */ 
00699         eeprom[i] = inw(ioaddr + Wn0EepromData);
00700       }
00701 
00702     }//EL3WINDOW(0) configuration finished
00703 
00704     /* EEPROM can be checksummed in order to assure that reading was OK */
00705     for (i = 0; i < 0x18; i++)
00706       checksum ^= eeprom[i];
00707     checksum = (checksum ^ (checksum >> 8)) & 0xff;
00708     if (checksum != 0x00) {             /* Grrr, needless incompatible change 3Com. */
00709       while (i < 0x21)
00710         checksum ^= eeprom[i++];
00711       checksum = (checksum ^ (checksum >> 8)) & 0xff;
00712     }
00713     if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
00714       printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
00715     
00716     /* Save HW address into dev_addr (MAC address in format 00:04:75:bd:ea:e7) */
00717     for (i = 0; i < 3; i++)
00718       ((u16 *)rt_3c905c_vp.dev_addr)[i] = htons(eeprom[i + 10]);
00719     
00720     /* This writes into the StationAddress register the NIC's HW address in order */
00721     /* to define the individual destination address that the NIC responds to when */
00722     /* receiving packets                                                          */
00723     EL3WINDOW(2);
00724     for (i = 0; i < 6; i++)
00725       outb(rt_3c905c_vp.dev_addr[i], ioaddr + i);
00726 
00727     EL3WINDOW(4);
00728     step = (inb(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
00729 
00730     if (dev && vci->drv_flags & HAS_CB_FNS) {
00731       unsigned long fn_st_addr;                 /* Cardbus function status space */
00732       unsigned short n;
00733       
00734       fn_st_addr = pci_resource_start (dev, 2);
00735       if (fn_st_addr) {
00736         rt_3c905c_vp.cb_fn_base = ioremap(fn_st_addr, 128);
00737         retval = -ENOMEM;
00738         if (!rt_3c905c_vp.cb_fn_base)
00739           goto free_ring;
00740       }
00741 
00742       EL3WINDOW(2);
00743       
00744       n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
00745       if (rt_3c905c_vp.drv_flags & INVERT_LED_PWR)
00746         n |= 0x10;
00747       if (rt_3c905c_vp.drv_flags & INVERT_MII_PWR)
00748         n |= 0x4000;
00749       outw(n, ioaddr + Wn2_ResetOptions);
00750     }
00751 
00752     /* Extract our information from the EEPROM data. */
00753     rt_3c905c_vp.info1 = eeprom[13];
00754     rt_3c905c_vp.info2 = eeprom[15];
00755     rt_3c905c_vp.capabilities = eeprom[16];
00756  
00757     if (rt_3c905c_vp.info1 & 0x8000){
00758       rt_3c905c_vp.full_duplex = 1;
00759       printk(KERN_INFO "Full duplex capable\n");
00760     }
00761 
00762     {
00763       unsigned int config;
00764       EL3WINDOW(3);
00765 
00766       /* This reads the MediaOptions register which shows what physical media */
00767       /* connections are available in the NIC                                 */
00768       rt_3c905c_vp.available_media = inw(ioaddr + Wn3_Options); //Wn3_Options = 8 vp.available_media = 0xa
00769 
00770       if ((rt_3c905c_vp.available_media & 0xff) == 0)           /* Broken 3c916 */
00771         rt_3c905c_vp.available_media = 0x40;
00772 
00773       /* This reads the InternalConfig register which provides a way to set */
00774       /* NIC-specific, non-host-related configuration settings              */ 
00775       config = inl(ioaddr + Wn3_Config); //Wn3_Config = 0
00776 
00777       rt_3c905c_vp.default_media = XCVR(config);
00778       if (rt_3c905c_vp.default_media == XCVR_NWAY)
00779         rt_3c905c_vp.has_nway = 1;
00780       rt_3c905c_vp.autoselect = AUTOSELECT(config);
00781     }
00782 
00783     if (rt_3c905c_vp.media_override != 7) {
00784       rt_3c905c_vp.if_port = rt_3c905c_vp.media_override;
00785     } else
00786       rt_3c905c_vp.if_port = rt_3c905c_vp.default_media;
00787 
00788     if (rt_3c905c_vp.if_port == XCVR_MII || rt_3c905c_vp.if_port == XCVR_NWAY) {
00789       int phy, phy_idx = 0;
00790       EL3WINDOW(4);
00791       mii_preamble_required++;
00792       mii_preamble_required++;
00793       rtl_3COM905C_mdio_read(24, 1);
00794       for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
00795         int mii_status, phyx;
00796         
00797         /*
00798          * For the 3c905CX we look at index 24 first, because it bogusly
00799          * reports an external PHY at all indices
00800          */
00801         if (phy == 0)
00802           phyx = 24;
00803         else if (phy <= 24)
00804           phyx = phy - 1;
00805         else
00806           phyx = phy;
00807         mii_status = rtl_3COM905C_mdio_read(phyx, 1);
00808         if (mii_status  &&  mii_status != 0xffff) {
00809           rt_3c905c_vp.phys[phy_idx++] = phyx;
00810           
00811           if ((mii_status & 0x0040) == 0)
00812             mii_preamble_required++;
00813         }
00814       }         
00815       mii_preamble_required--;
00816       if (phy_idx == 0) {
00817         rt_3c905c_vp.phys[0] = 24;
00818       } else {
00819         rt_3c905c_vp.advertising = rtl_3COM905C_mdio_read(rt_3c905c_vp.phys[0], 4);
00820         if (rt_3c905c_vp.full_duplex) {
00821           /* Only advertise the FD media types. */
00822           rt_3c905c_vp.advertising &= ~0x02A0;
00823           rtl_3COM905C_mdio_write(rt_3c905c_vp.phys[0], 4, rt_3c905c_vp.advertising);
00824         }
00825       }
00826     }
00827     if (rt_3c905c_vp.capabilities & CapBusMaster) {
00828       rt_3c905c_vp.full_bus_master_tx = 1;
00829       
00830       rt_3c905c_vp.full_bus_master_rx = (rt_3c905c_vp.info2 & 1) ? 1 : 2;
00831       rt_3c905c_vp.bus_master = 0;              /* AKPM: vortex only */
00832     }
00833     if (rt_3c905c_vp.pdev && rt_3c905c_vp.enable_wol) {
00834       rt_3c905c_vp.pm_state_valid = 1;
00835       rt_pci_save_state(dev, rt_3c905c_vp.power_state);
00836       rtl_3COM905C_acpi_set_WOL();
00837     }
00838     vortex_open(dev);
00839 
00840   }// if(dev)
00841     
00842   return 0;
00843 
00844  free_ring:
00845 
00846   pci_free_consistent(dev, sizeof(struct boom_rx_desc) * RX_RING_SIZE, rt_3c905c_vp.rx_ring, rt_3c905c_vp.rx_ring_dma);
00847   pci_free_consistent(dev, sizeof(struct boom_tx_desc) * TX_RING_SIZE, rt_3c905c_vp.tx_ring, rt_3c905c_vp.tx_ring_dma);
00848 
00849   return -1;
00850 
00851  free_region:
00852   if (rt_3c905c_vp.must_free_region){
00853     release_region(ioaddr, vci->io_size);
00854     rt_3c905c_vp.must_free_region = 0;
00855   }
00856   printk("vortex_probe1 fails.  Returns %d\n", retval);
00857 
00858   return -1;
00859 }


Data Structures
struct	boom_rx_desc
struct	boom_tx_desc
struct	media_table
struct	vortex_chip_info
struct	vortex_private
Defines
#define	DRV_NAME "3c59x"
#define	DRV_VERSION "0.1"
#define	DRV_RELDATE "27 december 2002"
#define	MAX_THREADS 10
#define	COM3_VENDOR_ID 0x10B7
#define	COM3_DEVICE_ID 0X9200
#define	BFEXT(value, offset, bitcount) ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
#define	BFINS(lhs, rhs, offset, bitcount)
#define	RAM_SIZE(v) BFEXT(v, 0, 3)
#define	RAM_WIDTH(v) BFEXT(v, 3, 1)
#define	RAM_SPEED(v) BFEXT(v, 4, 2)
#define	ROM_SIZE(v) BFEXT(v, 6, 2)
#define	RAM_SPLIT(v) BFEXT(v, 16, 2)
#define	XCVR(v) BFEXT(v, 20, 4)
#define	AUTOSELECT(v) BFEXT(v, 24, 1)
#define	EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
#define	EL3_CMD 0x0e
#define	EL3_STATUS 0x0e
#define	TX_RING_SIZE 16
#define	RX_RING_SIZE 32
#define	PKT_BUF_SZ 1536
#define	MAX_ADDR_LEN 8
#define	LAST_FRAG 0x80000000
#define	DN_COMPLETE 0x00010000
#define	DO_ZEROCOPY 0
#define	PCI_DEBUG 0
#define	EEPROM_CONTENTS_DEBUG 0
#define	MAC_ADDRESS_DEBUG 0
#define	FUNCTION_CALL_DEBUG 0
#define	INITIALIZATION_DEBUG 0
#define	RECEIVE_DEBUG 0
#define	PACKET_DATA_DEBUG 0
#define	INTERRUPT_DEBUG 0
#define	TRANSMIT_DEBUG 0
#define	ERROR_DEBUG 1
#define	SIGALRM2 RTL_SIGUSR1
#define	DEBUG(x, y) if(x) printk y
Enumerations
enum	vortex_cmd { TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, UpStall = 6<<11, UpUnstall = (6<<11)+1, DownStall = (6<<11)+2, DownUnstall = (6<<11)+3, RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, SetTxThreshold = 18<<11, SetTxStart = 19<<11, StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11, StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11 }
enum	RxFilter { RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 }
enum	vortex_status { IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004, TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, IntReq = 0x0040, StatsFull = 0x0080, DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10, DMAInProgress = 1<<11, CmdInProgress = 1<<12 }
enum	Window1 { TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14, RxStatus = 0x18, Timer = 0x1A, TxStatus = 0x1B, TxFree = 0x1C }
enum	Window0 { Wn0EepromCmd = 10, Wn0EepromData = 12, IntrStatus = 0x0E }
enum	Win0_EEPROM_bits { EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0, EEPROM_EWENB = 0x30, EEPROM_EWDIS = 0x00 }
enum	eeprom_offset { PhysAddr01 = 0, PhysAddr23 = 1, PhysAddr45 = 2, ModelID = 3, EtherLink3ID = 7, IFXcvrIO = 8, IRQLine = 9, NodeAddr01 = 10, NodeAddr23 = 11, NodeAddr45 = 12, DriverTune = 13, Checksum = 15 }
enum	Window2 { Wn2_ResetOptions = 12 }
enum	Window3 { Wn3_Config = 0, Wn3_MAC_Ctrl = 6, Wn3_Options = 8 }
enum	Window4 { Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt = 8, Wn4_Media = 10 }
enum	Win4_Media_bits { Media_SQE = 0x0008, Media_10TP = 0x00C0, Media_Lnk = 0x0080, Media_LnkBeat = 0x0800 }
enum	Window7 { Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12 }
enum	MasterCtrl { PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c, TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38 }
enum	rx_desc_status { RxDComplete = 0x00008000, RxDError = 0x4000, IPChksumErr = 1<<25, TCPChksumErr = 1<<26, UDPChksumErr = 1<<27, IPChksumValid = 1<<29, TCPChksumValid = 1<<30, UDPChksumValid = 1<<31 }
enum	tx_desc_status { CRCDisable = 0x2000, TxDComplete = 0x8000, AddIPChksum = 0x02000000, AddTCPChksum = 0x04000000, AddUDPChksum = 0x08000000, TxIntrUploaded = 0x80000000 }
enum	xcvr_types { XCVR_10baseT = 0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx, XCVR_100baseFx, XCVR_MII = 6, XCVR_NWAY = 8, XCVR_ExtMII = 9, XCVR_Default = 10 }
enum	ChipCaps { CapBusMaster = 0x20, CapPwrMgmt = 0x2000 }
enum	pci_flags_bit { PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4, PCI_ADDR0 = 0x10<<0, PCI_ADDR1 = 0x10<<1, PCI_ADDR2 = 0x10<<2, PCI_ADDR3 = 0x10<<3 }
enum	{ IS_VORTEX = 1, IS_BOOMERANG = 2, IS_CYCLONE = 4, IS_TORNADO = 8, EEPROM_8BIT = 0x10, HAS_PWR_CTRL = 0x20, HAS_MII = 0x40, HAS_NWAY = 0x80, HAS_CB_FNS = 0x100, INVERT_MII_PWR = 0x200, INVERT_LED_PWR = 0x400, MAX_COLLISION_RESET = 0x800, EEPROM_OFFSET = 0x1000, HAS_HWCKSM = 0x2000 }
enum	vortex_chips { CH_3C590 = 0, CH_3C592, CH_3C597, CH_3C595_1, CH_3C595_2, CH_3C595_3, CH_3C900_1, CH_3C900_2, CH_3C900_3, CH_3C900_4, CH_3C900_5, CH_3C900B_FL, CH_3C905_1, CH_3C905_2, CH_3C905B_1, CH_3C905B_2, CH_3C905B_FX, CH_3C905C, CH_3C980, CH_3C9805, CH_3CSOHO100_TX, CH_3C555, CH_3C556, CH_3C556B, CH_3C575, CH_3C575_1, CH_3CCFE575, CH_3CCFE575CT, CH_3CCFE656, CH_3CCFEM656, CH_3CCFEM656_1, CH_3C450 }
Functions
pci_dev *	rtl_3COM905C_init_device (void)
int	rtl_3COM905C_start_up_device (struct pci_dev *dev)
void	rtl_3COM905C_mdio_write (int phy_id, int location, int value)
int	rtl_3COM905C_mdio_read (int phy_id, int location)
void	rtl_3COM905C_mdio_sync (long ioaddr, int bits)
int	vortex_open (struct pci_dev *dev)
void	vortex_up (struct pci_dev *dev)
void	rtl_3COM905C_issue_and_wait (int cmd)
void	rtl_3COM905C_set_rx_mode (void)
void	rtl_3COM905C_acpi_set_WOL (void)
int	boomerang_rx (struct pci_dev *dev)
void	vortex_down (struct pci_dev *dev)
void	vortex_error (struct pci_dev *dev, int status)
int	vortex_close (struct pci_dev *dev)
void	vortex_remove_one (struct pci_dev *pdev)
int	rt_3c905c_send_packet (const char *buffer, size_t size)
void	rt_3c905c_send_signal (void)
int	rtl_3COM905C_open (struct rtl_file *filp)
int	rtl_3COM905C_release (struct rtl_file *filp)
ssize_t	rtl_3COM905C_write (struct rtl_file filp, const char buf, size_t count, loff_t *ppos)
int	rtl_3COM905C_ioctl (struct rtl_file *filp, unsigned int request, unsigned long other)
ssize_t	rtl_3COM905C_read (struct rtl_file filp, char buf, size_t count, loff_t *ppos)
Variables
vortex_chip_info	vortex_info
media_table	media_tbl []
char	mii_preamble_required
const int	mtu = 1500
int	max_interrupt_work = 32
const int	rx_copybreak = 200

rtl_3c905cx_drv.h File Reference

Data Structures

Defines

Enumerations

Functions

Variables

Define Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation